1. Field of the Invention
The present invention relates to an optical device and method to perform an asynchronous parallel and free-space processing of a N bits serial stream of an optical digital signal.
2. Description of the Related Art
Owing to the wide development of optical communication system, there is felt to be a need to design a device capable of processing digital information of an optical signal at a high rate.
Electronics, the technology employed so far to process optical signal, is going to become a bottleneck in optical communication systems and networks because electronic apparatuses have a narrow bandwidth compared to the optical bandwidth available in fiber optical communication system and are usually based on serial data processing.
The employment of optics in data processing is being studied to overcome this limitations. Potentially, processing apparatuses based on optical technology have a larger bandwidth and are transparent to data bit-rate, data format and transmission encoding. Other advantages of optics versus electronics can also be exploited like, for example, electromagnetic interference immunity, low skew, absence of impedance-matching problems.
Furthermore, an important and peculiar property of optics, completely absent in electronics, is the spatial bandwidth. This property can be an important advantage for optical processing systems. In optical architectures, space can be used freely, with the only limitation of diffraction phenomena.
Spatial bandwidth has important implications in optical processing system design, since it opens the way to parallel architectures wherein each signal carrying a parallel data stream travels through a spatial channel. This may overcome the so called "Von Neumann bottleneck" which affects conventional serial architectures. That is, the interconnection system (the bus) must be time-shared among all the processing elements. This forces most of the elements to be idle most of the time. In optic parallel systems, instead, optical interconnection must not be time-shared any more, thus overcoming such bottleneck.
U.S. Pat. No. 4,764,889 discloses an optical logic arrangement comprising a plurality of reflection holograms positioned in a two-dimensional array for optically interconnecting a similar plurality of optically nonlinear self electro-optic effect devices also positioned in a two-dimensional array. Each self electro-optic effect device is responsive to control light beams received on either side of the device array for emitting an output light beam that is a nonlinear function of the control light beams.
U.S. Pat. No. 4,926,366 discloses an optical integration technique using thin film technology which is based on a nonlinear interface with a diffusive or saturated Kerr-like nonlinearity. Solid state multiplexing is implemented with thin film multi-layer stacks resulting in polarizers and phase retarders matched to the interface.
U.S. Pat. No. 5,050,117 discloses optical computing cells or logic cells which are constructed of two or more spatial light rebroadcasters (SRL's). Data or information images in the form of light are written into and read from the SRL's with the SRL's being controlled to process the data in a desired manner.
U.S. Pat. No. 5,297,068 discloses an architecture for an optical computing apparatus which utilizes global free space smart optical interconnects and is based on a digital logic family derived from augmenting semiconductor technology with optical logic. The apparatus comprises input means, control means and detector means.
U.S. Pat. No. 5,497,261 discloses synchronization apparatus for an optical communication network. Such apparatus includes a delay member applying delays to signals received in an optical form, which form is that of an optical-type carrier wave carrying the signals. The delays are controlled so that the signals are synchronized on reference instants.
U.S. Pat. No. 5,446,571 discloses an optical code recognition unit (OCRU) for recognizing a predetermined n-bit optical code sequence coded using the Manchester code format, having an n-way splitter with an input and n parallel outputs. A plurality of gates are associated with the splitter outputs, respective pairs of splitter outputs leading to each of the gates via a respective optical combiner, and any remaining single splitter output leading directly to its gate. Each of the splitter outputs is subjected to a different delay of m half bit periods, where m=0 to 2(n-1), the value of m being chosen such that, if a predetermined optical code sequence is applied to the splitter input, the "1"s in the outputs of each of the pairs of splitter outputs reach the associated AND gates and the "1" in any remaining single splitter output reaches its AND gate at predetermined times such that all the gates are turned on.
EP Patent No. 0 742 660 A1 discloses a signal processor for the processing of digital signal in the physical (for example, optical) domain. This is inter alia relevant for Asynchronous Transfer Mode (ATM) systems in which control codes such as Virtual Path Identifiers (VPIs) and Virtual Channel Identifiers (VCIs) at the inputs of subsystem have to be changed. A symbol stream is lead through different delay branches. The number of delay branches is of such magnitude that at each moment, in at least one of the branches, both a "1" symbol and a "0" symbol is available. By the controlled opening and closing of the switches the symbol values can be changed.
WO 93/14604 discloses an optical code recognition unit (OCRU) for recognizing a predetermined n-bit optical code having an n-way splitter with an input and n parallel outputs. A plurality of combiners are associated with the splitter outputs, and a respective gate is controlled by the output of each of the combiners. Each of the splitter outputs is subjected to a different delay of from 0 to (n-1) bit periods, and each combiner receives an input from at least one of the splitter outputs. The OCRU is such that all the gates are turned on if a predetermined optical code is applied to the splitter input.
WO 95/33324 discloses a packet carried on an optical network which is routed by carrying out a logic operation on an address word carried in a packet header, and a predetermined discriminator word. A binary routing decision is made in accordance with the product of the logic operation.
Pei T. B. et al., "High-speed parallel CRC circuits in VLSI", IEEE Transactions on Communications, 40, No. 4, 653-657 (1992) investigate the use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems. The Authors show that parallel architectures fall somewhat short of ideal speedups in practice, but they should still enable current CMOS technologies to go well beyond 1 Gb/s data rates.
The above mentioned disclosure relates to synchronous optical signal processing.
The present invention aims at exploiting the above mentioned advantages offered by optics with an optical device and a method to perform an asynchronous parallel and free-space processing of a N bits serial stream of an optical digital signal.